This application relies for priority upon Korean Patent Application No. 2001-35110, filed on Jun. 20, 2001, the contents of which are herein incorporated by reference in their entirety.
The present invention relates to an integrated circuit devices and a methods of fabricating the same, and more particularly, to integrated circuit device structures and methods for forming contact holes.
FIG. 1 is a cross-sectional view of a general semiconductor device having a self-alignment contact pad. Referring to FIG. 1, an isolation layer 12, which defines an active region, is formed in a predetermined region on a semiconductor substrate 10 through a general shallow trench isolation (STI) method. Next, a gate electrode 18 is formed on a predetermined portion of the semiconductor substrate 10 having an active region and the isolation layer 12. The gate electrode 18 can be formed by depositing a gate insulating layer 14, a conductive layer 15, a capping layer 16, and a spacer 17 which is formed along the sidewalls of the gate insulating layer 14, the conductive layer 15 and the capping layer 16, on the semiconductor substrate 10. Thereafter, a junction region 20 is formed by implanting impurities into the active region on both sides of the gate electrode 18. A contact pad 22 is formed in a self-aligned manner between the gate electrode 18 and another gate electrode to contact the junction region 20, and an interlevel insulating layer 24 is then formed on the resultant structure. A photoresist pattern exposing the contact pad 22 is formed through a conventional photolithography process on the upper surface of the interlevel insulating layer 24. A contact hole 26 is obtained by etching the exposed interlevel insulating layer 24 using the photoresist pattern as a mask. A conductive layer is then formed on the exposed contact pad 22.
As integrated circuit memory devices are made more highly integrated, the widths of the metal wirings and contact pads generally decrease in proportion to the increase in integration. Decreased widths of the metal wiring and contact pads can considerably increase the difficulty of forming a properly aligned contact hole therewith. Moreover, small contact hole areas can be difficult to fill with a conductive layer and a void may occur in the contact hole. Example misalignment of a contact hole in the interlevel insulating layer is shown in FIG. 1 by the dotted lines 28.
An integrated circuit device according to some embodiments of the present invention includes a semiconductor substrate having a conductive region and an insulating region, a conductive pad on the conductive region of the semiconductor substrate, an auxiliary pad adjacent to and electrically isolated from the conductive pad, an interlevel insulating layer on the semiconductor substrate and in which a contact hole is defined which exposes at least a portion of both the conductive pad and the auxiliary pad.
An integrated circuit device according to other embodiments of the present invention includes a semiconductor substrate having an active region and an isolation layer region, a gate electrode at a predetermined position on the semiconductor substrate, a junction region on the active region at a side of the gate electrode, a contact pad on the junction region, an auxiliary pad on the isolation layer region adjacent to the contact pad, and an interlevel insulating layer on the semiconductor substrate and in which a contact hole is defined which exposes at least a portion of the contact pad and the auxiliary pad.
An integrated circuit device according to still other embodiments of the present invention includes a semiconductor substrate having a conductive region, an underlayer on the semiconductor substrate, a primary metal wiring on the underlayer in electrical contact with the conductive region, an auxiliary metal wiring on the underlayer and adjacent to the primary metal wiring, and an interlevel insulating layer on the semiconductor substrate and in which a via hole is defined which exposes at least a portion of the primary metal wiring and the auxiliary metal wiring.
In a method of fabricating an integrated circuit device according to some embodiments of the present invention, a conductive pad is formed on the conductive region of a semiconductor substrate having a conductive region and an insulating region. An auxiliary pad is formed on a region adjacent to the conductive pad. An interlevel insulating layer is formed on the semiconductor substrate and across the conductive pad and the auxiliary pad. A contact hole is formed in the interlevel insulating layer to at least partially expose both the conductive pad and the auxiliary pad.
The contact hole or via hole can be sufficiently large to expose both the conductive pad and the auxiliary pad. To enable high integration density, the auxiliary pad can be formed close to the conductive pad so that it is substantially exposed by the contact hole. Exposing the auxiliary pad with the contact pad can enable the contact hole to be substantially larger than the contact pad alone and simplify alignment of a photoresist mask pattern which is used to form the contact hole. A larger contact hole provides an increased contact area which in-turn can simplify subsequent processes for filling of the contact hole, such as with an upper wiring, and avoid voids within the contact hole.
The effect of misalignment when the contact hole or via hole is formed can be reduced by forming the auxiliary pad adjacent to and electrically isolated from the contact pad. In particular, the hole can be larger which can simplify alignment of a mask for forming the hole. Moreover, a larger hole can provide an increased contact area which in-turn can simplify subsequent processes for filling the hole without voids.